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xicor, inc. 1994, 1995, 1996 patents pending 9900-3002.11 2/24/99 ep 1 characteristics subject to change without notice 4k novram/eeprom cpu supervisor with novram and output ports features 4kbit serial eeprom 400khz serial interface speed 16-byte page write mode one nibble novram 120ns novram access speed autostore direct/bus access of novram bits four output ports operates at 3.3v +/- 10% low voltage reset when vcc < 3v. output signal shows low voltage condition activates novram autostore. internal block on eeprom operation max eeprom/novram nonvolatile write cycle: 5ms high reliability 1,000,000 endurance cycles guaranteed data retention: 100 years 20-l tssop package description the low voltage X4C105 combines several functions into one device. the ?st is a 2-wire, 4kbit serial eeprom memory with write protection. a write protect (wp) pin provides hardware protection for the upper half of this memory against inadvertent writes. a one nibble novram is provided and occupies a single location. this allows access of 4 bits in a single 150ns cycle. this is useful for tracking system operation or process status. the novram memory is completely isolated from the serial memory section. a low voltage detect circuit activates a reset pin when vcc drops below 3v. this signal also blocks new read or write operations and initiates a novram autostore. the autostore operation is powered by an external capacitor to ensure that the value in the novram is always maintained in the event of a power failure. the four novram bits also appear on four seperate output pins to allow continuous control of external circuitry, such as asics. xicor eeproms are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. device block diagram command decode and control logic hv generation timing and control eeprom array x decoder y decoder data register write control logic wp scl sda s1 s2 d0 d1 d2 d3 ce oe we i/o buffers control logic and timing static ram memory eeprom memory vcc vss reset voltage monitor power on reset low voltage detect cap supply o0 o1 o2 o3 output- buffers and latches 4 bits X4C105
X4C105 2 package/pinouts pin names: vss ground sda serial data vcc power scl serial clock wp write protect s1, s2 device select inputs cap external autostore capacitor d0-d3 novram i/os reset low voltage detect output ce novram chip enable oe novram read signal we novram write signal o0-o3 novram outputs device description serial memory section the device contains a 4k-bit eeprom memory array with an internal address counter that allows it to be read sequentially, through its entire address space after receiving only 1 full address. the serial interface includes a current address read that requires no input address, but allows reading of the entire array starting from the address plus one of the last read or write. the address counter is also used for the write operation where the user may enter up to a page of data (16 bytes) after supplying only 1 full address. a wp pin provides hardware write protection. the wp pin active (high) prevents writes to the top half of the memory. this section is a 4k-bit version of an industry standard 24c03 device. novram section the X4C105 also contains a single nibble of novram, with parallel access. this memory is completely isolated from the serial memory section. the novram is intended to connect to the system memory bus and uses standard ce , oe , and we pins to control access. a novram (or nonvolatile ram) consists of an sram part and an eeprom part. the sram is saved to eeprom only when power fails and the eeprom is recalled to sram only on power up. output ports the X4C105 has four output only ports. these are active whenever power is applied to the device. the state of the output pin re?cts the value in the respective sram bit. as such, these port pins provide a nonvolatile state. the conditions on the pins are restored when power is re- applied to the device. this can be valuable as a dip switch replacment for controlling the conditions of an asic or other system logic. low voltage detection when the internal low voltage detect circuitry senses that vcc is low, several things happen: the reset pin goes active. the contents of the sram are automatically saved to the ?hadow eeprom. internal circuitry switches to provide power for the autostore operation from the cap pin so the store operation can complete even in the event of a cata- strophic power failure. to insure this, it is recom- mended that a 47uf capacitor be used on the cap pin. the capacitor is continuously charged during normal operation to provide the necessary charge to complete the store operation. other internal circuits are turned off to minimize current consumption dur- ing the store operations. communication to the device is interrupted and any command is aborted. if a serial nonvolatile store is in progress when power fails, the operation is com- pleted and is followed by a novram autostore cycle. capacitor backup circuit the diagram in figure1 shows a representation of the capacitor backup circuit. s1 o0 v cc sda scl cap wp s2 reset ce we oe d0 d3 d2 d1 v ss o1 o2 o3 3 2 4 1 18 19 17 20 7 6 8 5 14 15 13 16 9 10 12 11 20l tssop
X4C105 3 s erial interface serial interface conventions the device supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see ?ure 2. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see ?ure 3. start novram autostore to internal voltage supply high when v cc > v trip low when v cc X4C105 4 serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see ?ure 3. serial acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to ?ure 4. the device will respond with an acknowledge after recognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identi?r and/or select bits are incorrect or when the device is busy, such as during a nonvolatile write. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. scl sda start stop figure 3. valid start and stop conditions scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge figure 4. acknowledge response from receiver
X4C105 5 serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see ?ure 5. an attempted write to a protected block of memory will suppress the acknowledge bit and the operation will terminate. page write the device is capable of a page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the ?st data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?olls over and goes back to ? on the same page. this means that the master can write 16 bytes to the page starting at any location on that page. if the master begins writing at location 10, and loads 12 bytes, then the ?st 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. afterwards, the address counter would point to location 7 of the page that was just written. see ?ure 6. if the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time. address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 figure 6. writing 12 bytes to a 16-byte page starting at location 10. s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 figure 5. byte write sequence
X4C105 6 the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to ?ure 7 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing the write. the contents of the array will not be affected. s t a r t s t o p slave address byte address data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 < n < 16) figure 7. page write operation
X4C105 7 acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indicate the end of the masters byte load operation, the device initiates the internal non volatile write cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to the ?w chart in figure 8. serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the device contains an address counter that maintains the address of the last word read incremented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power up, the address of the address counter is unde?ed, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to ?ure 9 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. random read a random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address byte. after acknowledging receipts of the word address byte, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to ?ure 10 for the address, acknowledge, and data transfer sequence. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes figure 8. acknowledge polling sequence
X4C105 8 the device offers a similar operation, called ?et current address, where the device ends the transmission and issues a stop instead of the second start, shown in ?ure 10. the device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will then read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the ?st data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. at the end of the address space the counter ?olls over to address 0000 h and the device continues to output data for each acknowledge received. refer to ?ure 11 for the acknowledge and data transfer sequence. serial device addressing slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: a device type identi?r that is always ?010? two bits that provide the device select bits. one bit that becomes the msb of the address. one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte de?es the opera- tion to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 12. s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 figure 9. current address read sequence 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master figure 10. random address read sequence
X4C105 9 s t o p a c k a c k a c k data (2) slave address data (n) a c k sda bus signals from the slave signals from the master 1 data (n-1) (n is any integer greater than 1) data (1) figure 11. sequential read sequence after loading the entire slave address byte from the sda bus, the device compares the device select bits with the status of the device select pins. upon a correct compare, the device outputs an acknowledge on the sda line. figure 12. slave byte word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is unde?ed on a power up condition. write protect operations the wp pin provides write protection. the wp pin protects the upper half of the array. table 1. write protected areas 1010s2s1a8r/w wp pin serial memory write protection low writes possible to all locations high no writes to 100h-1ffh, writes possible to 000h to 0ffh
X4C105 10 absolute maximum ratings temperature under bias .......................-65?c to +135?c storage temperature .............................-65?c to +150?c voltage on any pin with respect to ground .-1.0v to 7.0v dc output current.................................................. 5 ma lead temperature (soldering, 10 seconds) ......... 300?c stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating characteristics. dc operating characteristics v cc = 3.0 to 3.6v at -40?c to +85?c unless otherwise specified. symbol parameter min. max. unit test conditions i cc1 (1) active supply current serial read or serial write (does not include the nonvolatile store operation) 2.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, f scl = 400khz, sda = read/write operation ce , oe , we , d0-d3 = v ih ; o0-o3, reset = open cap is tied to vcc; vcc > vtrip i cc2 (1) average active supply current during serial nonvol- aitle store operation 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda =v ih ; wp, s1, s2 =v il ce , oe , we , d0-d3= v ih ; o0-o3, reset = open cap is tied to vcc. test during the n.v. write cycle. i cc3 (1) active supply current vola- tile novram read 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda =v ih ; wp, s1, s2 =v il we = v ih ; ce , oe = v il d0-d3, o0-o3, reset = open cap is tied to vcc; vcc > vtrip i cc4 (1) active supply current vola- tile novram write 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda =v ih ; wp, s1, s2 =v il oe = v ih ; ce , we = v il d0-d3 = v il or v ih , o0-o3, reset = open cap is tied to vcc; vcc > vtrip i cc5 (1) average active supply cur- rent over novram store, or active current during recall 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda =v ih ; wp, s1, s2 =v il we , ce , oe = v ih ; d0-d3, o0-o3, reset = open cap is tied to vcc vcc < vtrip for store; vcc > vtrip for recall i sb1 (2) standby current 50 m a v il = v cc x 0.1, v ih = v cc x 0.9 scl, sda, ce , we , oe , d0-d3, = v ih , wp=v il o0-o3, reset = open; cap is tied to vcc i li input leakage current 10 m a v in = gnd to v cc
X4C105 11 notes: 1. the device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. 2. the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits i n the slave address byte. 3. v il min. and v ih max. are for reference only and are not tested. capacitance t a = 25?c, f = 1.0 mhz, v cc = 3.0-3.6v notes: 1. this parameter is periodically sampled and not 100% tested. serial nonvolatile write cycle timing 1. t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. i lo output leakage current 10 m a v sda = gnd to v cc; device is in standby (2) v il (3) input low voltage -0.5 v cc x 0.3 v v ih (3) input high voltage v cc x 0.7 v cc +0.5 v v hys schmitt trigger input hysteresis .05 x vcc v v ol output low voltage 0.4 v i ol = 2.0ma, vcc=3.3v v oh output high voltage vcc-0.4 v i oh = -1ma, vcc=3.3v symbol parameter max. units test conditions c i/o (1) input/output capacitance (sda, d0-d3, o0-o3) 8 pf v i/o = 0v c in (1) input capacitance (scl, wp, ce , we , oe , s1, s2) 6 pf v in = 0v symbol parameter min. typ.(1) max. units t wc (1) write cycle time 3 5 ms dc operating characteristics. dc operating characteristics v cc = 3.0 to 3.6v at -40?c to +85?c unless otherwise specified. symbol parameter min. max. unit test conditions
X4C105 12 serial memory ac characteristics serial ac t est conditions equivalent ac output load circuit for v cc = 3.0-3.6v input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load sda 1533 w 100pf 3.3v for v ol = 0.4v and i ol = 2ma serial ac specifications t a = -40?c to +85?c, v cc = +3.0v to +3.6v, unless otherwise specified . notes: 1. this parameter is periodically sampled and not 100% tested. 2. cb = total capacitance of one bus line in pf. symbol parameter 400khz option units min. max. f scl scl clock frequency 0 400 khz t in pulse width of spikes to be suppressed by the input filter 0 50 ns t aa scl low to sda data out valid 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 1.3 m s t low clock low time 1.3 m s t high clock high time 0.6 m s t su:sta start condition setup time 0.6 m s t hd:sta start condition hold time 0.6 m s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 m s t su:sto stop condition setup time 0.6 m s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (2) 300 ns t f sda and scl fall time 20 +.1cb (2) 300 ns t su: s1, s2,wp s1, s2, and wp setup time 0.4 ms t hd: s1, s2,wp s1, s2, and wp hold time 0.4 ms cb capacitive load for each bus line 400 pf
X4C105 13 serial timing diagrams bus timing s1, s2, and wp pin timing write cycle timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd: s1,s2,wp scl sda in s1, s2, and wp t su: s1,s2,wp clk 1 clk 9 slave address byte start scl sda t wc 8th bit of last byte ack stop condition start condition
X4C105 14 novram ac characteristics novram ac conditions of test novram equivalent a.c load circuits input pulse levels vcc x 0.1 to vcc x 0.9 input rise and fall times 10ns input and output timing levels vcc x 0.5 3.3v 30pf 1596 w 3093 w novram read cycle specifications: table 3. novram read cycle limits notes: 1. t lz and t olz min.; t soe and t hoe min; and t hz and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with cl = 5pf, from the point when ce or oe return high (whichever occurs ?st) to the time when the outptus are no longer driven. symbol parameter vcc = 3.0v-3.6v -40 o c to +85 o c units min. max. t rc read cycle time 120 ns t ce chip enable access time 50 ns t oe output enable access time 50 ns t oh output hold from ce or oe high 0 ns t wes write enable high setups time 25 ns t weh write enable high hold time 25 ns t lz (1) chip enable to output in low z 0 ns t olz (1) output enable to output in low z 0 ns t hz (1) chip disable to output in high z 0 50 ns t ohz (1) output disable to output in high z 0 50 ns t soe (1) oe setup prior to operation in 2-wire mode 100 ms t hoe (1) oe hold following operation in 2-wire mode 100 ms
X4C105 15 novram read cycle novram write cycle specifications: novram write cycle limits vcc = 3.0v-3.6v, t a = -40 o c to +85 o c 1. t lz and t olz min.; t soe and t hoe min; and t hz and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with cl = 5pf, from the point when ce or oe return high (whichever occurs ?st) to the time when the outputs are no longer driven. symbol parameter min. max. units t wc write cycle time 120 ns t wc1 write cycle time 170 ns t oes output enable high setup time 50 ns t oeh output enable high hold time 50 ns t cw chip enable to end of write input 50 ns t ce write setup time 0 ns t ch write hold time 0 ns t wp write pulse width 50 ns t wp1 write pulse width 100 ns t wph write pulse high recovery time 50 ns t ds data setup to end of write 40 ns t dh data hold time 0 ns t ndo new data output 50 ns t soe (1) oe setup prior to operation in 2-wire mode 100 ms t hoe (1) oe hold following operation in 2-wire mode 100 ms t wz write enable to output in high-z 50 ns t ow output active from end of write 0 ns t chz (1) chip disable to output in high z 0 50 ns t ohz (1) output disable to output in high z 0 50 ns t ohz t hz t ce t oe t olz t lz oe ce we d0-d3 t wes t weh t oh t rc
X4C105 16 novram we controlled write cycle novram ce controlled write cycle t cw t oeh t dh t ce t wp t ds oe we d0-d3 ce t oes t ch t wc t wph (data i/o) o0-o3 (data out) previous valid data t ndo new valid data data valid t cw t dh t wp t ds oe we ce data valid t oeh t oes t ce t ch t wph t wc o0-o3 (data out) previous valid data t ndo new valid data d0-d3 (data in)
X4C105 17 low voltage detect/power cycle parameters low voltage detect and output pin recall symbols parameters min. typ. max. unit v trip reset trip voltage 2.80 2.875 2.95 v t rpd v cc detect to reset active 500 ns t purst power up reset time-out delay (t purst option 1) - default 100 200 400 ms t f v cc fall time from vcc=3v to vcc=2.5v 100 m s t r v cc rise time from vcc=2.5v to vcc=3v 100 m s t ovt output pins valid after vcc exceeds vtrip 200 ns v rvalid reset valid v cc 1v v b brownout voltage - if vcc goes below v b , vcc must go to 0v before being re-applied. 2v v cc v trip rst t purst t purst t r t f t rpd v rvalid o0-o3 data valid v cc (min) t ovt t ovt data valid v b
X4C105 18 ordering information v cc limits blank = 3.3v ?0% temperature range blank = commercial = 0? to +70? i = industrial = ?0? package v20 = 20 lead tssop device X4C105 x x ? part mark convention 20-lead tssop eyww xxx blank = 3.3v ?0%, 0 to +70? i = 3.3 ?0%, -40 to +85? X4C105 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,88 3, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detec- tion and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup- port device or system, or to affect its safety or effectiveness.

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